The MyHDL manual

• Overview
• Background information
  • Prerequisites
  • A small tutorial on generators
  • About decorators
• Introduction to MyHDL
  • A basic MyHDL simulation
  • Signals and concurrency
  • Parameters, ports and hierarchy
  • Terminology review
  • Some remarks on MyHDL and Python
  • Summary and perspective
• Hardware-oriented types
  • The intbv class
  • Bit indexing
  • Bit slicing
  • The modbv class
  • Unsigned and signed representation
• Structural modeling
  • Introduction
  • Conditional instantiation
  • Converting between lists of signals and bit vectors
  • Inferring the list of instances
• RTL modeling
  • Introduction
  • Combinatorial logic
  • Sequential logic
  • Finite State Machine modeling
• High level modeling
  • Introduction
  • Modeling with bus-functional procedures
  • Modeling memories with built-in types
  • Modeling errors using exceptions
  • Object oriented modeling
• Unit testing
  • Introduction
  • The importance of unit tests
  • Unit test development
• Co-simulation with Verilog
  • Introduction
  • The HDL side
  • The MyHDL side
  • Restrictions
  • Implementation notes
• Conversion to Verilog and VHDL
  • Introduction
  • Solution description
  • Features
  • The convertible subset
  • Conversion of lists of signals
  • Conversion of Interfaces
  • Assignment issues
  • Excluding code from conversion
  • User-defined code
  • Template transformation
  • Conversion output verification by co-simulation
  • Conversion of test benches
  • Methodology notes
  • Known issues
• Conversion examples
  • Introduction
  • A small sequential design
  • A small combinatorial design
  • A hierarchical design
  • Optimizations for finite state machines
  • RAM inference
  • ROM inference
  • User-defined code
• Reference
  • Simulation
  • Modeling
  • Co-simulation
  • Conversion to Verilog and VHDL
  • Conversion output verification